 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 1 - 1. general description ak0991 5 is 3 - axis electronic compass ic with high sensitive hall sensor technology. small package of ak09915 incorporates magnetic sensors for detecting terrestrial magnetism in the x - axis, y - axis, and z - axis, a sensor driving circuit, signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. self - test function is also incorpo rated. from its compact foot print and thin package feature, it is suitable for map heading up purpose in gps - equipped smart phone and tablet to realize pedestrian navigation function. 2. features ? functions: ? 3 - axis magnetometer device suitable for compass a pplication ? built - in a to d converter for magnetometer data out ? 16 - bit data out for each 3 - axis magnetic component ? sensitivity: 0. 15 t/lsb (typ.) ? serial interface ? i 2 c bus interface standard, fast and high - speed mode s (up to 2.5 mhz) compliant with philips i 2 c specification ver.2.1 ? 4 - wire spi ? operation mode ? power - down, single measurement, continuous measurement and self - test ? drdy function for measurement data ready ? magnetic sensor overflow monitor function ? built - in os cillator for internal clock source ? power on reset circuit ? self - test function with internal magnetic source ? built - in noise suppression filter (nsf) ? selectable sensor drive ? low power drive / low noise drive ? built - in magnetic sensitivity adjustment circuit ? 32 fifo data buffer ? operating temperatures: ? - 30?c to +85?c ? operating supply voltage: ? analog power supply +1.7v to +3.6v ? digital interface supply +1.65v to analog power supply voltage ? current consumption: ? power - down: 3 a (typ.) ? measurement: ? average current consumption at 100 hz repetition rate ? low power drive : 0 . 9 ma (typ.) ? low noise drive : 1. 8 ma (typ.) ? package: ? ak0991 5 c 14 - pin wl - csp (bga): 1.6 mm ? 1.6 mm ? 0.5 mm (typ.) ak0991 5 3 - axis electronic compass
[ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ................................ ... 1 2. features ................................ ................................ ................................ ................................ ...................... 1 3. table of contents ................................ ................................ ................................ ................................ ....... 2 4. block diagram and functions ................................ ................................ ................................ .................... 4 5. pin configurations and functions ................................ ................................ ................................ .............. 5 6. absolute maximum ratings ................................ ................................ ................................ ....................... 6 7. recommended operating conditions ................................ ................................ ................................ ........ 6 8. electrical characteristics ................................ ................................ ................................ ........................... 6 8.1. dc characteristics ................................ ................................ ................................ .............................. 6 8.2. ac characteristics ................................ ................................ ................................ .............................. 7 8.3. a nalog circuit characteristics ................................ ................................ ................................ ............ 8 8.4. 4 - wire spi ................................ ................................ ................................ ................................ ............ 9 8.5. i 2 c bus interface ................................ ................................ ................................ ............................... 10 9. fun ctional descriptions ................................ ................................ ................................ ........................... 13 9.1. power states ................................ ................................ ................................ ................................ ...... 13 9.2. reset functions ................................ ................................ ................................ ................................ . 13 9.3. operation modes ................................ ................................ ................................ ............................... 14 9.4. description of each operation mode ................................ ................................ ............................... 15 9.4.1. power - down mode ................................ ................................ ................................ .................... 15 9.4.2. single measurement mode ................................ ................................ ................................ ........ 15 9.4.3. continuous measurement mode 1, 2, 3, 4, 5 and 6 ................................ ................................ ... 16 9.4.4. self - test mode ................................ ................................ ................................ ........................... 19 9.5. noise suppression filter (nsf) ................................ ................................ ................................ ........ 19 9.6. sensor drive select ................................ ................................ ................................ ........................... 19 9.7. fifo ................................ ................................ ................................ ................................ .................. 20 9.7.1. watermark ................................ ................................ ................................ ................................ . 20 10. serial interface ................................ ................................ ................................ ................................ ...... 21 10.1. 4 - wire spi ................................ ................................ ................................ ................................ .......... 21 10.1.1. writing data ................................ ................................ ................................ .............................. 21 10.1.2. reading data ................................ ................................ ................................ ............................. 22 10.2. i 2 c bus interface ................................ ................................ ................................ ............................... 22 10.2.1. data transfer ................................ ................................ ................................ ............................. 22 10.2.2 . write instruction ................................ ................................ ................................ .................... 25 10.2.3. read instruction ................................ ................................ ................................ ...................... 25 10.2.4. high - speed mode (hs - mode) ................................ ................................ ................................ .... 27 11. registers ................................ ................................ ................................ ................................ ................ 28 11.1. description of registers ................................ ................................ ................................ .................... 28 11.2. register map ................................ ................................ ................................ ................................ ..... 29 11.3. detailed description of registers ................................ ................................ ................................ ..... 30 11.3.1. wia: who i am ................................ ................................ ................................ ........................ 30 11.3.2 . rsv: reserved ................................ ................................ ................................ .......................... 30 11.3.3. info: information ................................ ................................ ................................ ..................... 30 11.3.4. st1: status 1 ................................ ................................ ................................ ............................. 30 11.3.5. hxl to hzh: measurement magnetic data ................................ ................................ .............. 31 11.3.6. tmps: dummy ................................ ................................ ................................ .......................... 32 11.3.7. st2: status 2 ................................ ................................ ................................ ............................. 32 11.3.8. cntl1: control 1 ................................ ................................ ................................ ..................... 33 11.3.9. cntl2: control 2 ................................ ................................ ................................ ..................... 34 11.3.10. cntl3: control 3 ................................ ................................ ................................ ..................... 34 11 .3.11. ts1, ts2, ts3: test ................................ ................................ ................................ .................. 35 11.3.12. i2cdis: i 2 c disable ................................ ................................ ................................ .................. 35 [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 3 - 11.3.13. ts4: test ................................ ................................ ................................ ................................ ... 35 11.3.14. asax,asay,asaz: dummy ................................ ................................ ................................ .. 35 11.3.15. tph1,tph2,rr,syt,dt: test ................................ ................................ ................................ . 36 12. example of recommended external connection ................................ ................................ ................. 37 12.1. i 2 c bus interface ................................ ................................ ................................ ............................... 37 12.2. 4 - wire spi ................................ ................................ ................................ ................................ .......... 38 13. package ................................ ................................ ................................ ................................ ................. 39 13.1. marking ................................ ................................ ................................ ................................ ............. 39 13.2. pin assignment ................................ ................................ ................................ ................................ . 39 13.3. ou tline dimensions ................................ ................................ ................................ ........................... 40 13.4. recommended foot print pattern ................................ ................................ ................................ ..... 40 14. relationship between the magnetic field and output code ................................ ................................ 41 important notice ................................ ................................ ................................ ................................ ... 42 [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 4 - 4. block diagram and functions block function 3 - axis hall sensor monolithic hall elements. mux multiplexer for selecting hall elements. chopper sw performs chopping. he - drive magnetic sensor drive circuit for constant - current driving of sensor. pre - amp fixed - gain differential amplifier used to amplify the magnetic sensor signal. integrator & adc integrates and amplifies pre - amp output or t - sensor output and performs analog - to - digital conversion. osc1 generates an operating clock for sensor measurement. osc2 generates an operating peri odic clock for sequencer. por power o n reset circuit. generates reset signal on rising edge of vdd. vref generates reference voltage and current. fifo the buffer is capable up to 32 sets of data . interface logic & register exchanges data with an external cpu. drdy pin indicates sensor measurement has ended and data is ready to be read. i 2 c bus interface using two pins, namely, scl and sda. standard, fast and high - speed mode s are supported. the low - voltage specification can be supported by applying 1.65v to the vid pin. 4 - wire spi is also supported by sk, si, so and csb pins. 4 - wire spi works in vid pin voltage down to 1.65 v, too. signal processing noise suppression function by the filtering process. filtering process can be enabled or disabled. timing control generates a timing signal required for internal operation from a clock generated by the osc1. magnetic source generates magnetic field for self - test of magnetic sensor. 3 - axis hall sensor mux sda/si drdy chopper sw he - drive pre - amp integrator & adc interface, l ogic & register scl/sk vdd v ref timing control vid so osc1 csb magnetic source cad0 vss por cad1 rstn signal processing osc 2 fifo [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 5 - 5. pin configurations and functions pin no. pin name i/o power supply type function a1 drdy o vid cmos data ready output pin. h active. informs measurement ended and data is ready to be read. a2 csb i vid cmos chip select pin for 4 - wire spi. l active. connect to vid when selecting i 2 c bus interface. a3 scl i vid cmos when the i 2 c bus interface is selected (csb pin is connected to vid). scl: control clock input pin input: schmitt trigger sk when the 4 - wire spi is selected. sk: serial clock input pin. a4 sda i/o vid cmos when the i 2 c bus interface is selected (csb pin is connected to vid). sda: control data input/output pin input: schmitt trigger, output: o pen - drain si i when the 4 - wire spi is selected. si: serial data input pin b1 vdd - - power positive power supply pin. b3 n/c - - - non - connect connect to vss or keep this pin non - connected. b4 so o vid cmos when the i 2 c bus interface is selected (csb pin is connected to vid) hi - z output. keep this pin electrically non - connected. when the 4 - wire spi is selected. serial data output pin c1 vss - - power ground pin c2 n/c - - - non - connect connect to vss or keep this pin non - connected. c3 n/c - - - non - connect connect to vss or keep this pin non - connected. c4 vid - - power digital interface positive power supply pin. d1 cad0 i vdd cmos when the i 2 c bus interface is selected (csb pin is connected to vid) cad0:slave address 0 input pin connect to vss or vdd. when the 4 - wire serial interface is selected. connect to vss. d2 cad1 i vdd cmos when the i 2 c bus interface is selected (csb pin is connected to vid). cad1:slave address 1 input pin connect to vss or vdd. when the 4 - wire serial interface is selected. connect to vss. d4 rstn i vid cmos reset pin. resets registers by setting to l. connect to vid when not in use. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 6 - 6. absolute maximum ratings vss = 0v parameter symbol min. max. unit power supply voltage (vdd, vid) v+ - 0.3 +4.3 v input voltage ( except for power supply pin) vin - 0.3 v+ +0.3 v input current (except for power supply pin) iin - 10 ma storage temperature t st - 40 +125 ?c if the device is used in conditions exceeding these values, the device may be destroyed. normal operations are not guaranteed in such exceeding conditions. 7. recommended operating conditions vss = 0v parameter remark symbol min. typ. max. unit operating temperature ta - 30 +85 ?c power supply voltage vdd pin voltage vdd 1.7 3.0 3.6 v vid pin voltage vid 1.65 vdd v 8. electrical characteristics the following conditions apply unless otherwise noted: vdd = 1.7v to 3.6v, vid = 1.65v to vdd, temperature range = - 30 ?c to + 85 ?c 8.1. dc characteristics parameter symbol pin condition min. typ. max. unit high level input voltage 1 vih1 csb rstn 70%vid v low level input voltage 1 vil1 30%vid v high level input voltage 2 vih2 sk/scl si/sda 70%vid vid+0.3 v low level input voltage 2 vil2 - 0.3v 30%vid v high level input voltage 3 vih3 cad0 cad1 70%vdd v low level input voltage 3 vil3 30%vdd v input current 1 iin1 sk/scl si/sda csb rstn v in = vss or vid - 10 +10 a cad0 cad1 v in = vss or vdd - 10 +10 hysteresis input voltage (note 1) vhs scl sda vid2v 5%vid v vid<2v 10%vid high level output voltage 1 (note 2) voh1 so drdy ioh - 100a 80%vid v low level output voltage 1 (note 2) vol1 iol 1 +100a 20%vid v low level output voltage 2 (note 2) (note 3) vol2 sda iol 2 +3ma vid2v 0.4 v iol 2 +3ma vid<2v 20%vid v (note 1) schmitt trigger input (reference value for design) . (note 2) ioh: high level output current. iol1/iol2: low level output current. (note 3) output is open - drain. connect to a pull - up resistor externally. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 7 - parameter symbol pin condition min. typ. max. unit current consumption (note 4) idd1 vdd vid power - down mode vdd = vid = 3.0v 3 6 a idd2 when magnetic sensor is driven 2 .1 3.5 ma idd3 self - test mode 3.2 4.7 ma idd 4 (note 5) 0.1 5 a (note 4) without any resistance load (note 5) (case 1) vdd = on, vid = on, rstn pin = l . (case 2) vdd = on, vid = off (0v), rstn pin = l. (case 3) vdd = o ff (0v), vid = o n . 8.2. ac characteristics parameter symbol pin condition min. typ. max. unit power supply rise time psup vdd vid period of time that vdd (vid) changes from 0.2v to vdd (vid). 50 ms por completion time (note 6) port period of time after psup to power - down mode (note 7) 1 00 s power supply turn off voltage (note 6) sdv vdd vid turn off voltage to enable por to restart (note 7) 0.2 v power supply turn on interval (note 6) psint vdd vid period of time that voltage lower than sdv needed to be kept to enable por to restart (note 7) 100 s wait time before mode setting twa i t 100 s reset input effective pulse width ( l ) trstl rstn 5 s (note 6) reference value for design. (note 7) when por circuit detects the rise of vdd/vid voltage, it resets internal circuits and initializes the registers. after reset, ak0991 5 transits to power - down mode. psint psup p ort power - down mode sdv twa i t v dd /v id 0v power - down mode vil trstl [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 8 - 8.3. analog circuit characteristics parameter symbol condition min. typ. max. unit measurement data output bit dbit - 16 - b it time for measurement tsm single measurement mode sdr bit = 0 (refer to 9.6 ) 4.5 m s sdr bit = 1 (refer to 9.6 ) 8.5 magnetic sensor sensitivity bse t a = 25 ?c 0. 1425 0. 15 0. 1575 t/lsb magnetic sensor measurement range (note 8) brg t a = 25 ?c 4 670 4912 5160 t magnetic sensor initial offset (note 9) t a = 25 ?c - 2 000 + 2 000 lsb (note 8) reference value for design . (note 9) value of measurement data register on shipment test without applying magnetic field on purpose. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 9 - 8.4. 4 - wire spi 4 - wire spi is compliant with mode 3 (spi - mode3). parameter symbol min. typ. max. unit clock frequency fspi 4 mhz csb setup time tcs 50 ns data setup time ts 50 ns data hold time th 50 ns sk high time twh 100 ns sk low time twl 100 ns sk setup time tsd 50 ns sk to so delay time (note 10) tdd 50 ns csb to so delay time (note 10) tcd 50 ns sk rise time (note 11) tr 100 ns sk fall time (note 11) tf 100 ns csb high time tch 150 ns (note 10) so load capacitance: 20pf (note 11) reference value for design. [4 - wire spi] [rise time and fall time] csb sk si tcs s o ts tsd tcd th tdd hi - z hi - z twh twl tch sk tr tf 0.9vid 0.1vid [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 10 - 8.5. i 2 c bus interface csb pin = h i 2 c bus interface is compliant with standard mode , fast mode and high - speed mode (hs - mode) . standard/fast /hs - mode is selected automatically by fscl. ? standard mode fscl100khz symbol parameter min. typ. max. unit fscl scl clock frequency 100 khz thigh scl clock high time 4.0 s tlow scl clock low time 4.7 s tr sda and scl rise time 1.0 s tf sda and scl fall time 0.3 s thd:sta start condition hold time 4.0 s tsu:sta start condition setup time 4.7 s thd:dat sda hold time (vs. scl falling edge) 0 s tsu:dat sda setup time (vs. scl rising edge) 250 ns tsu:sto stop condition setup time 4.0 s tbuf bus free time 4.7 s ? fast mode 100 k hzfscl400khz symbol parameter min. typ. max. unit fscl scl clock frequency 400 khz thigh scl clock high time 0.6 s tlow scl clock low time 1.3 s tr sda and scl rise time 0.3 s tf sda and scl fall time 0.3 s thd:sta start condition hold time 0.6 s tsu:sta start condition setup time 0.6 s thd:dat sda hold time (vs. scl falling edge) 0 s tsu:dat sda setup time (vs. scl rising edge) 100 ns tsu:sto stop condition setup time 0.6 s tbuf bus free time 1.3 s tsp noise suppression pulse width 50 ns [i 2 c bus interface timing] 1 / fscl scl vih 2 vil 2 thigh scl sda v ih 2 t low tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto v il2 v ih2 v il2 tsp [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 11 - ? high - speed mode (hs - mode) ? cb100pf (cb: load capacitance) fsclh2.5mhz symbol parameter min. typ. max. unit fsclh sclh clock frequency 2.5 mhz thigh sclh clock high time 110 ns tlow sclh clock low time 220 ns tr_cl sclh rise time 10 40 ns tr_cl1 sclh rise time after a repeated start condition and after an acknowledge bit 10 80 ns tr_da sdah rise time 10 80 ns tf_cl sclh fall time - 40 ns tf_da sdah fall time - 80 ns thd:sta start condition hold time 160 ns tsu:sta start condition setup time 160 ns thd:dat sdah hold time (vs. sclh falling edge) 0 ns tsu:dat sdah setup time (vs. sclh rising edge) 10 ns tsu:sto stop condition setup time 160 ns tsp noise suppression pulse width 10 ns ? cb 4 00pf fsclh 1.7 mhz symbol parameter min. typ. max. unit fsclh sclh clock frequency 1.7 mhz thigh sclh clock high time 120 ns tlow sclh clock low time 320 ns tr_cl sclh rise time 20 80 ns tr_cl1 sclh rise time after a repeated start condition and after an acknowledge bit 20 160 ns tr_da sdah rise time 20 160 ns tf_cl sclh fall time - 80 ns tf_da sdah fall time - 160 ns thd:sta start condition hold time 160 ns tsu:sta start condition setup time 160 ns thd:dat sdah hold time (vs. sclh falling edge) 0 ns tsu:dat sdah setup time (vs. sclh rising edge) 10 ns tsu:sto stop condition setup time 160 ns tsp noise suppression pulse width 10 ns [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 12 - [i 2 c bus interface timing of hs - mode] vih2 vil2 vih2 vil2 sdah sclh start start stop t f_d a t r_d a tr_cl1 t r_cl1 t r_cl tf_cl thigh tlow thigh thd;dat tsu;dat tsu;sto tsu;sta thd;sta sclh vih2 vil2 1/fsclh [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 13 - 9. functional descriptions 9.1. power states when vdd and vid are turned on from vdd = off (0v) and vid = off (0v), all registers in ak0991 5 are initialized by por circuit and ak0991 5 transits to power - down mode. all the states in the table below can be set, although the transition from state 2 to state 3 and the transition from state 3 to state 2 are prohibited. table 9 . 1 power states s tate vdd vid power state 1 off (0v) off (0v) off (0v). it doesnt affect external interface. digital input pins other than scl and sda pin should be fixed to l it doesnt affect external interface. it doesnt affect external interface. digital input pins other than scl and sda pin should be fixed to l 9.2. reset functions when the power state is on, always keep vidvdd. power on r eset (por) works until vdd reaches to the operation effective voltage (about 1.1v: reference value for design) on power - on sequence. when vdd = 1.7 to 3.6v, por circuit and vid monitor circuit are active. when vid = 0v, ak0991 5 is in reset status and it consumes the current of reset state (idd 4 ). ak0991 5 has four types of reset; (1) power on r eset (por) when vdd rise is detected, por circuit operates, and ak09915 is reset. (2) vid monitor when vid is turned off (0v), ak0991 5 is reset. (3) reset pin (rstn) ak0991 5 is reset by reset pin. when reset pin is not used, connect to vid. (4) soft reset ak0991 5 is reset by setting srst bit. after reset is completed , all registers and fifo buffer are initialized and ak09915 transit s to p ower - down mode automat ically . [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 14 - 9.3. operation modes ak0991 5 has following nine operation modes: (1) power - down mode (2) single measurement mode (3) continuous measurement mode 1 (4) continuous measurement mode 2 (5) continuous measurement mode 3 (6) continuous measurement mode 4 (7) continuous measurement mod e 5 (8) continuous measurement mode 6 (9) self - test mode by setting cntl2 register s mode[4:0] bits, the operation set for each mode is started. a transition from one mode to another is shown below. figure 9 . 1 operation mode when power is turned on, ak09915 is in power - down mode. when a specified value is set to mode[4:0] bits , ak09915 transits to the specified mode and starts operation. when user wants to change operation mode, transit to power - down mode first and then transit to other modes. after power - down mode is set, at least 100 s (twa i t) is needed before setting another mode . mode[ 4 :0] bits = 00 0 0 1 mode[ 4 :0] bits = 0000 0 transits automatically mode[4:0] bits = 00010 mode[4:0] bits = 00000 mode[4:0] bits = 00100 mode[4:0] bits = 00000 mode[4:0] bits = 00110 mode[4:0] bits = 00000 mode[4:0] bits = 01000 m ode[4:0] bits = 00000 v mode[4:0] bits =01 01 0 mode[4:0] bits = 00000 mode[4:0] bits = 01 10 0 mode[4:0] bits = 00000 mode[4:0] bits = 10000 mode[4:0] bits = 00000 transits automatically power - down mode continuous measurement mode 2 sens or is measured periodically in 2 0hz. transits to power - down mode by writing mode[ 4 :0]=00 0 00 . self - test mode sensor is self - tested and the result is output. transits to power - down mode automatically. single measurement mode sensor is measured for one time and data is output. transits to power - down mode automatically after measurement ended. continuous measurement mode 1 senso r is measured periodically in 1 0 hz. transits to power - down mode by writing mode[ 4 :0] = 0000 0 . continuous measurement mode 3 sens or is measured periodically in 5 0hz. transits to power - down mode by writing mode[ 4 :0]=00 0 00 . continuous measurement mode 4 senso r is measured periodically in 10 0hz. transits to power - down mode by writing mode[ 4 :0]=00 0 00 . continuous measurement mode 5 sens or is measured periodically in 200 hz. transits to power - down mode by writing mode[ 4 :0]=00 0 00 . continuous measurement mode 6 sensor is measured periodically i n 1 hz. transits to power - down mode by writing mode[ 4 :0]=00 0 00 . [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 15 - 9.4. description of each operation mode 9.4.1. power - down mode power to almost all internal circuits is turn ed off. all registers are accessible in power - down mode. data stored in read/write registers are remained. they can be reset by soft reset. 9.4.2. single measurement mode when single measurement mode ( mode[4:0] bits = 00001) is set, magnetic sensor measurement is started. after magnetic sensor measurement and signal processing is finished, measurement magnetic data is stored to measurement data registers (hxl to hzh), then ak0991 5 transits to power - down mode automatically. on transition to power - down mode, mode [4:0] bits turns to 00000. at the same time, drdy bit in st1 register turns to 1. this is called data ready. when any of measurement data register s (hxl to tmps) or st2 register is read, drdy bit turns to 0. it remains 1 on transition from power - down mode to another mode. drdy pin is in the same state as drdy bit. ( figure 9 . 2 ) when sensor is measuring (measurement period), measurement data registers (hxl to tmps) keep the previous data. therefore, it is possible to read out data even in measurement period. data read out in measurement period are previous dat a. ( figure 9 . 3 ) figure 9 . 2 single measurement mode when data is read out of measurement per iod figure 9 . 3 single measurement mode when data read started during measurement period operation mode: single measuremnet power-down (1) (2) (3) measurement period measurement data register last data measurement data (1) data(2) data(3) drdy data read data(1) data(3) register write mode[4:0]="00001" mode[4:0]="00001" mode[4:0]="00001" operation mode: single measuremnet power-down (1) (2) (3) measurement period measurement data register last data measurement data (1) data(3) drdy data read data(1) register write mode[4:0]="00001" mode[4:0]="00001" mode[4:0]="00001" [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 16 - 9.4.3. continuous measurement mode 1, 2, 3 , 4, 5 and 6 when continuous measurement mode s ( 1 to 6) are set, magnetic sensor measurement is started periodically at 10 hz, 20 hz, 50 hz , 100 hz , 200 hz and 1hz respectively. after magnetic sensor measurement and signal processing is finished, measurement magnetic data is stored to measurement data re gisters (hxl to hzh) and all circuits except for the minimum circuit required for counting cycle length are turned off (pd). when the next measurement timing comes, ak0991 5 wakes up automatically from pd and starts measurement again. continuous measurement mode ends when power - down mode ( mode[4:0] bits = 00000) is set. it repeats measurement until power - down mode is set. when continuous measurement mode s ( 1 to 6) are set again while ak0991 5 is already in continuous measurement mode, a new meas urement starts. st1, st2 and measurement data registers (hxl to tmps) will not be initialized by this. table 9 . 2 continuous measurement modes operation mode register setting (mode[4:0] bits) measurement frequency [hz] continuous measurement mode 1 00010 10 continuous measurement mode 2 00100 20 continuous measurement mode 3 00110 50 continuous measurement mode 4 01000 100 continuous measurement mode 5 01010 200 continuous measurement mode 6 01100 1 figure 9 . 4 continuous measurement mode 9.4.3.1. data ready when measurement data is stored and ready to be read, drdy bit in st1 register turns to 1. this is called data ready. drdy pin is in the same state as drdy bit. when measurement is performed correctly, ak0991 5 becomes data ready on transition to pd after measurement. (n-1)th nth (n+1)th pd measurement pd measurement pd 10hz,20hz,50hz,100hz,200hz and 1hz [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 17 - 9.4.3.2. normal read sequence (1)check data ready or not by any of the following method. polling drdy bit of st1 register monitor drdy pin when data ready, proceed to the next step. (2)read st1 register ( not needed when polling st1) drdy: shows data ready or not. not when 0, data ready when 1. dor: shows if any data has been skipped before the current data or not. there are no skipped data when 0, there are skipped data when 1. (3)read measurement data when any of measurement data register s (hxl to tmps) or st2 register is read, ak0991 5 judges that data reading is started. when data reading is started, drdy bit and dor bit turns to 0. (4)read st2 register (required) hofl: shows if magnetic sensor is overflowed or not. 0 means not overflowed, 1 means overflowed. when st2 register is read, ak0991 5 judges that data reading is finished. stored measurement data is protected during data reading and data is not updated. by reading st2 register, this p rotection is released. it is required to read st2 register after data reading. figure 9 . 5 normal read sequence 9.4.3.3. data read start during measurem e nt when sensor is measuring (measurement period), measurement data registers (hxl to tmps) keep the previous data. therefore, it is possible to read out data even in measurement period. if data is started to be read during measurement period, previous data is read. figure 9 . 6 data read start during measuring (n-1)th nth (n+1)th pd measurement pd measurement pd measurement data register (n-1)th nth (n+1)th drdy data read st1 data(n) st2 st1 data(n+1) st2 (n-1)th nth (n+1)th pd measurement pd measurement pd measurement data register (n-1)th nth drdy data read st1 data(n) st2 st1 data(n) st2 [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 18 - 9.4.3.4. data skip when nth data was not read before (n+1)th measurement ends, data ready remains until data is read. in this case, a set of measurement data is skipped so that dor bit turns to 1. when data reading started after nth measurement ended and did not finish reading before (n+1)th measurement ended, nt h measurement data is protected to keep correct data. in this case, a set of measurement data is skipped and not stored so that dor bit turns to 1. in both case, dor bit turns to 0 at the next start of data reading. figure 9 . 7 data skip: when data is not read figure 9 . 8 data skip: when data read has not been finished before the next measurement end 9.4.3.5. end op eration set power - down mode ( mode[4:0] bits = 00000) to end continuous measurement mode. (n-1)th nth (n+1)th pd measurement pd measurement pd measurement data register (n-1)th nth (n+1)th drdy dor data read st1 data(n+1) st2 (n-1)th nth (n+1)th (n+2)th pd measurement pd measurement pd measurement pd measurement data register (n-1)th nth (n+2)th data register is protected because data is being read not data ready drdy because data is not updated (n+1)th data is skipped dor data read st1 datan st2 st1 data(n+2) [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 19 - 9.4.3.6. magnetic sensor overflow ak0991 5 has the limitation for measurement range that the sum of absolute values of each axis should be smaller than 4912 t. (note 12) |x|+|y|+|z| < 4912 t when the magnetic field exceeded this limitation, data stored at measurement data are not correct. this is called magnetic sensor overflow. when magnetic sensor overflow occurs, hofl bit turns to 1. when measurement data register (hxl to hzh) is updated, hofl bit is updated. (note 12) bse : 0.15 t /lsb 9.4.4. self - test mode self - test mode is used to check if the magnetic sensor is working normally. when self - test mode ( mode[4:0] bits = 10000) is set, magnetic field is generated by the internal magnetic source and magnetic sensor is measured. measurement data is stored to measurement data registers (hxl to hzh), then ak09915 transits to power - down mode automatically. data read sequence and functions of read - only registers in self - test mode is the same as single measurement mode. 9.4.4.1. self - test sequence (1)set power - down mode. ( mode[4:0] bits = 00000) (2)set self - test mode. ( mode[4:0] bits = 10000) ( 3)check data ready or not by any of the following method. polling drdy bit of st1 register monitor drdy pin when data ready, proceed to the next step. (4)read measurement data (hxl to hzh) 9.4.4.2. self - test judgment when measurement data read by the above sequenc e is in the range of following table, ak0991 5 is working normally. hx[15:0] bits hy[15:0] bits hz[15:0] bits criteria - 200 hx + 200 - 200 h y + 200 - 8 00 h z - 200 9.5. noise suppression filter (nsf) in single measurement mode, continuous measurement mode s (1 to 6) , output from the magnetic sensor can be filtered to suppress the noise. this filter name is noise suppression filter (nsf). when nsf bit = 0, nsf is disable and output magnetic data is not filtered. when nsf bit = 1, output magnetic data is filtered. nsf bit can be changed in power - down mode only. default nsf bit is disable (nsf bit = 0). 9.6. sensor drive select ak09915 can choose low power or low noise drive. low power is used to save the current consumption and low noise is used to reduce the noise of the ak09915. when low power ( sdr bit = 0) is set, average current consumption at 100 hz repetition rate is reduced from 1. 8 ma to 0.9 ma. when low noise ( sdr bit = 1 ) is set , output magnetic data noise is less than low power (about 70% of low power ) . sdr bit can be changed in power - down mode only. default sdr bit is low power enable ( sdr bit = 0). [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 20 - 9.7. fifo fifo function is available in continuous measurement modes. f ifo function is enabled by setting fifo bit = 1 . it is prohibited to enable fifo function in any modes other than continuous measurement modes. when fifo function is enabled, measurement magnetic d ata (hxl to hzh) and hofl bit are stored to the buffer a s a set of data. the buffer is capable up to 32 sets of data. if a new data is measured when 32 sets of data are already stored, the oldest data set is deleted and the new data set is stored. if measurement data registers are read when fifo function is ena bled, the oldest data set is read as first - in first - out method. when reading out data from the buffer, always start with hxl register and finish with st2 register. by accessing hxl register, the oldest data set is loaded to the measurement data register s from the buffer. reading st2 register is regarded as the finish of reading out one set of data. t hen the read data set is deleted and the next oldest data set will be ready to be read. if st2 register or hxl register is not read, the same set of data is kept in the measurement data register s . when fifo function is enabled, drdy bit and dor bit functions differently. drdy bit informs that data set is stored up to w atermark. refer to 9.7.1 for details. dor bit informs that data set is overflowed from the buffer. if a set of new data is measured when the buffer is full, dor bit turns to 1 . if at least one data set is read from t he buffer, dor bit turns to 0 . if data is read out when the buffer is empty , inv bit is turned to 1 and measurement data registers (hxl to hz h) are forced to fixed value 7fffh. if a set of new data is measured, inv bit turns to 0 . when ak09915 is reset (refer to 9.2 ) , fifo buffer are initialized . 9.7.1. watermark when fifo function is enabled, watermark function is available. by setting wm[ 4 :0] bits, ak0991 5 info rms that data set is stored up to or more than watermark. if the number of stored data set is equal to or more than the number set to wm[ 4 :0] bit s, drdy bit turns to 1 . if the number of stored data set is less than the number set to wm[ 4 :0] bits, drdy bi t turns to 0 . drdy pin is the same state as drdy bit. wm[ 4 :0] bits should be changed in the power - down mode only. it is prohibited to write wm[ 4 :0] bits in other modes. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 21 - 10. serial interface ak0991 5 supports i 2 c bus interface and 4 - wire spi. a selection is made by csb pin. when used as 3 - wire spi, set si pin and so pin wired - or externally. csb pin = l: 4 - wire spi csb pin = h: i 2 c bus interface 10.1. 4 - wire spi the 4 - wire spi consists of four digital signal lines: sk, si, so, and csb, and is provided in 16bit protocol. data consists of read/write control bit (r/w), register address (7 - bit) and control data (8 - bit). to read out all axes measurement data (x, y, z), an option to read out more than one byte data using automatic increment comma nd is available. (sequential read operation) csb pin is low active. input data is taken in on the rising edge of sk pin, and output data is changed on the falling edge of sk pin. (spi - mode3) communication starts when csb pin transits to l and stops when csb pin transits to h. sk pin must be h during csb pin is in transition. also, it is prohibited to change si pin during csb pin is h and sk pin is h. 10.1.1. writing data input 16 bits data on si pin in synchronous with the 16 - bit serial clock input on s k pin. out of 16 bits input data, the first 8 - bit specify the r/w control bit (r/w = 0 when writing) and register address (7 - bit), and the latter 8 - bit are control data (8 - bit). when any of addresses listed on table 11 . 1 is input, ak09915 recognizes that it is selected and takes in latter 8 - bit as setting data. if the number of clock pulses is less than 16, no data is written. if the number of clock pulses is more th an 16, data after the 16th clock pulse on si pin are ignored. it is not compliant with serial write operation for multiple addresses. figure 10 . 1 4 - wire spi writing data csb sk si (input) 1 rw so (output) hi - z a6 6 a5 a4 a3 a2 a1 a0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d7 d6 d5 d4 d3 d2 d1 d0 [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 22 - 10.1.2. reading data input the r/w control bit (r/w = 1) and 7 - bit register address on si pin in synchronous with the first 8 - bit of the 16 bits of a serial clock input on sk pin. then ak09915 outputs the data held in the specified register with msb first from so pin. when clocks are input continuously after one byte of data is read, the address is incremented and data in the next address is output. accordingly, after the falling edge of the 15th clock and csb pin is l, the data in the next address is output on so pin. when csb pin is driven l to h, so pin is placed in the high - impedance state. ak09915 has three incr e m e n t ation lines; 00 h to 18 h , 30 h to 32 h and 60h to 62h . in line 00h to 18h, the incrementation depends on fifo bit. when fifo function is disabled, ak099 15 increments as follows: 00 h ? 01 h ? 02h ? 03h ? 10h ? 11h ... ? 18h ? 00h ? 01h . when fifo function is enabled : 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h ? 11 h ? 12 h ... . in line 30h to 32h and 60h to 62h, it increments as: 30 h ? 31 h ? 32 h ? 30 h , and 60 h ? 61 h ? 62 h ? 60 h . 33 h to 35 h and 37 h are reserved addresses. do not access to those addresses. when spe cified address is other than 00 h to 18 h , 30h to 37h and 60h to 62h, ak0991 5 recognizes that it is not selected and keeps so pin in high - impe dance state. therefore, user can use other addresses for other devices. figure 10 . 2 4 - wire spi reading data 10.2. i 2 c bus interface the i 2 c bus interface of ak0991 5 supports the standard mode (100 khz max.), the fast mode (400 khz max.), and high - speed mode (hs - mode, 2.5 mhz max.). 10.2.1. data transfer to access ak0991 5 on the bus, generate a start condition first. next, transmit a one - byte slave address including a device address. at this time, ak0991 5 compares the slave address with its own address. if these addresses match, ak0991 5 generates an acknowledgement, and then executes read or write instruction. at the end of instruction execution, generate a stop condition. csb sk si (input) 1 rw so (output) hi - z a6 6 a5 a4 a3 a2 a1 a0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d7 d6 d5 d4 d3 d2 d1 d0 hi - z [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 23 - 10.2.1.1. change of data a change of data on the sda line must be made during low period of the clock on the scl line. when the clock signal on the scl line is high, the state of the sda line must be stable. (data on the sda line can be changed only wh en the clock signal on the scl line is low.) during the scl line is high, the state of data on the sda line is changed only when a start condition or a stop condition is generated. figure 10 . 3 data change 10.2.1.2. start/stop condition if the sda line is driven to low from high when the scl line is high, a start condition is generated. every instruction starts with a start condition. if the sda line is driven to high from low when the scl line is high, a stop condition is generated. every instruction stops with a stop condition. figure 10 . 4 start and stop condition scl sda data line stable : data valid change of data allowed scl sda stop condition start condition [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 24 - 10.2.1.3. acknowledge the ic that is transmitti ng data releases the sda line (in the high state) after sending 1 - byte data. the ic that receives the data drives the sda line to low on the next clock pulse. this operation is referred as acknowledge. with this operation, whether data has been transferred successfully can be checked. ak0991 5 generates an acknowledge after reception of a start condition and slave address. when a write instruction is executed, ak0991 5 generates an acknowledge after every byte is received. when a read instruction i s executed, ak0991 5 generates an acknowledge then transfers the data stored at the specified address. next, ak0991 5 releases the sda line then monitors the sda line. if a master ic generates an acknowledge instead of a stop condition, ak0991 5 transmits the 8 - bit data stored at the next address. if no acknowledge is generated, ak0991 5 stops data transmission. figure 10 . 5 generation of acknowledge 10.2.1.4. slave address the slave address of ak0991 5 can be selected from the following list by setting cad0/1 pin. when cad pin is fixed to vss, the corresponding slave address bit is 0. when cad pin is fixed to vdd, the corresponding slave address bit is 1 . table 10 . 1 slave address and cad0/1 pin cad1 cad0 slave address 0 0 0c h 0 1 0d h 1 0 0e h 1 1 0f h msb lsb 0 0 0 1 1 cad1 cad0 r/w figure 10 . 6 slave address the first byte including a slave address is transmitted after a start condition, and an ic to be accessed is selected from the ics on the bus according to the slave address. when a slave address is transferred, the ic whose device address matches the transferred slave address genera tes an acknowledge then executes an instruction. the 8th bit (least significant bit) of the first byte is a r/w bit. when the r/w bit is set to 1, read instruction is executed. when the r/w bit is set to 0, write instruction is executed. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 25 - 10.2.2. write instruction when the r/w bit is set to 0, ak09915 performs write operation. in write operation, ak09915 generates an acknowledge after receiving a start condition and the first byte (slave address) then receives the second byte. the second byte is used t o specify the address of an internal control register and is based on the msb - first configuration. msb lsb a7 a6 a5 a4 a3 a2 a1 a0 figure 10 . 7 register address after receiving the second byte (register address), ak09915 generates an acknowledge then receives the third byte. the third and the following bytes represent control data. control data consists of 8 - bit and is based on the msb - first configuration. ak09915 generates an acknowledge after every byte is received. data transfer always stops with a stop condition generated by the master. msb lsb d7 d6 d5 d4 d3 d2 d1 d0 figure 10 . 8 control data ak09915 can write multiple bytes of data at a time. after reception of the third byte (control data), ak09915 generates an acknowledge then receives the next data. if additional data is received instead of a stop condition after receiving one byte of data, the ad dress counter inside the lsi chip is automatically incremented and the data is written at the next address. the address is incremented from 00 h to 18 h from 30 h to32 h , or from 60 h to 62 h . when the address is between 00 h and 18 h , in case that fifo function i s disabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h , and the address goes back to 00 h after 18 h . in case that fifo function is enabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h, and the address goes back to 11h after 18h. when the address is between 30 h and 32 h , the address goes back to 30 h after 32 h . when the address is between 30h and 32h, the address goes back to 30h after 32h. actual data is written only to read/write registers ( table 11 . 2 ) figure 10 . 9 write instruction 10.2.3. read instruction when the r/w bit is set to 1, ak09915 performs read operation. if a master ic generates an acknowledge instead of a stop condition after ak09915 transfers the data at a specified address, the data at the next address can be read. address can be 00 h to 18 h , 30 h to 32 h , or 60 h to 62 h . when the address is between 00 h and 18 h , in case that fifo function is disabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h , and the address goes back to 00 h after 18 h . in case that fifo function is enabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h , and the address goes back to 11h after 18 h . when the address sda s t a r t a c k a c k s slave address a c k register address(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k a c k r/w= " 0 " [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 26 - is between 30 h and 32 h , the address goes back to 30 h after 32 h . when the address is between 60 h and 62 h , the address goes back to 60 h after 62 h . ak09915 supports current address read and random address read . 10.2.3.1. current address read ak09915 has an address counter inside the lsi chip. in current address read operation, the data at an address specified by this counter is read. the internal address counter holds the next address of the most recently accessed address. for example, if the address most recently accessed (for read instruction) is address n, and a current address read operation is attempted, the data at address n+1 is read. in current address read operation, ak09915 generates an acknowledge after receiving a slave address for the read instruction (r/w bit = 1). next, ak09915 transfers the data specified by the internal address counter starting with the next clock pulse, then increments the internal counter by one. if the master ic generates a stop condition instead of an acknowl edge after ak09915 transmits one byte of data, the read operation stops. figure 10 . 10 current address read 10.2.3.2. random a ddress read by random address read operation, data at an arbitrary address can be read. the random address read operation requires to execute write instruction as dummy before a slave address for the read instruction (r/w bit = 1) is transmitted. in random read operation, a start co ndition is first generated then a slave address for the write instruction (r/w bit = 0) and a read address are transmitted sequentially. after ak09915 generates an acknowledge in response to this address transmission, a start condition and a slave addres s for the read instruction (r/w bit = 1) are generated again. ak09915 generates an acknowledge in response to this slave address transmission. next, ak09915 transfers the data at the specified address then increments the internal address counter by one. if the master ic generates a stop condition instead of an acknowledge after data is transferred, the read operation stops. figure 10 . 11 random address read sda s t a r t a c k a c k s slave address a c k data(n +1 ) d ata(n+ 2 ) p s t o p data(n+x) a c k d ata(n+ 3 ) a c k r/w= " 1 " sda s t a r t a c k a c k s slave address a c k register address(n) data(n +1 ) p s t o p data(n+x) a c k d ata(n+ 2 ) a c k r/w= " 0 " s t a r t a c k s slave address r/w= " 1 " [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 27 - 10.2.4. high - speed mode (hs - mode) ak09915 supports the hs - mode. hs - mode can only commence after the following conditions (all of which are in fast/standard - mode): ? start condition (s) ? 8 - bit master code (00001xxx) ? not - acknowledge bit () the diagram below shows data flow of the h s - mode. after start condition, feed master code 00001xxx for transfer to the hs - mode. and then ak09915 feeds back not - acknowledge bit and switch over to circuit for the hs - mode between times t1 and th. ak09915 can communicate at the hs - mode from next start condition. at time tfs, ak09915 switches its internal circuit from the hs - mode to the first mode with the stop condition (p). this transfer completes in the bus free time (tbuf). figure 10 . 12 data transfer format in hs - mode figure 10 . 13 hs - mode transfer [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 28 - 11. registers 11.1. description of registers ak09915 has registers of 2 9 addresses as indicated in table 11 . 1 . every address consists of 8 - bit data. data is transferred to or received from the external cpu via the serial interface described previously. table 11 . 1 register table name address read/ write description bit width remarks wia 1 00 h read company id 8 wia2 01 h read device id 8 rsv 02 h read reserved 8 info 03 h read information 8 st1 10 h read status 1 8 data status hxl 11 h read measurement magnetic data 8 x - axis data hxh 12 h read 8 hyl 13 h read 8 y - axis data hyh 14 h read 8 hzl 15 h read 8 z - axis data hzh 16 h read 8 tmps 17 h read dummy 8 dummy st2 18 h read status 2 8 data status cntl1 30 h read/write control 1 8 control settings cntl2 31 h read/write control 2 8 control settings cntl3 32 h read/write control 3 8 control settings ts1 33 h read/write test 8 do not access ts2 34 h read/write test 8 do not access ts3 35 h read/write test 8 do not access i2cdis 36 h read/write i 2 c disable 8 ts4 37 h read/write test 8 do not access asax 60h read dummy 8 dummy asay 61h read dummy 8 dummy asaz 62h read dummy 8 dummy tph1 c0h read/write test 8 do not access tph2 c1h read/write test 8 do not access rr c2h read/write test 8 do not access syt c3h read/write test 8 do not access dt c4h read/write test 8 do not access addresses 00 h to 18 h , 30 h to 32 h and 60h to 62h are compliant with automatic increment function of serial interface respectively. when the address is in 00 h to 18 h , in case that fifo function is disabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h , and the address goes back to 00 h after 18 h . in case that fifo function is enabled, the address is incremented 00 h ? 01 h ? 02 h ? 03 h ? 10 h ? 11 h ... ? 18 h , and the address goes back to 11h after 18 h. when the address is in 30 h to 32 h , the address goes back to 30 h after 32 h . when the address is in 6 0h to 6 2h, the address goes b ack to 6 0h after 6 2h. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 29 - 11.2. register map table 11 . 2 register map addr. register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 00 h wia1 0 1 0 0 1 0 0 0 01 h wia2 0 0 0 1 0 0 0 0 02 h rsv rsv 7 rsv 6 rsv 5 rsv 4 rsv 3 rsv 2 rsv 1 rsv 0 03 h info 0 0 0 0 0 0 0 0 10 h st1 hsm 0 0 0 0 0 dor drdy 11 h hxl hx7 hx6 hx5 hx4 hx3 hx2 hx1 hx0 12 h hxh hx15 hx14 hx13 hx12 hx11 hx10 hx9 hx8 13 h hyl hy7 hy6 hy5 hy4 hy3 hy2 hy1 hy0 14 h hyh hy15 hy14 hy13 hy12 hy11 hy10 hy9 hy8 15 h hzl hz7 hz6 hz5 hz4 hz3 hz2 hz1 hz0 16 h hzh hz15 hz14 hz13 hz12 hz11 hz10 hz9 hz8 17 h tmps 0 0 0 0 0 0 0 0 18 h st2 0 0 0 0 hofl inv 0 0 read/wri te register 30 h cntl1 0 0 nsf wm4 wm3 wm2 wm1 wm0 31 h cntl2 fifo sdr 0 mode4 mode3 mode2 mode1 mode0 32 h cntl3 0 0 0 0 0 0 0 srst 33 h ts1 - - - - - - - - 34 h ts2 - - - - - - - - 35 h ts3 - - - - - - - - 36 h i2cdis i2cdis7 i2cdis6 i2cdis5 i2cdis4 i2cdis3 i2cdis2 i2cdis1 i2cdis0 37 h ts4 - - - - - - - - read - only register 60h asax 1 0 0 0 0 0 0 0 61h asay 1 0 0 0 0 0 0 0 62h asaz 1 0 0 0 0 0 0 0 read/write register c0h tph1 - - - - - - - - c1h tph2 - - - - - - - - c2h rr - - - - - - - - c3h syt - - - - - - - - c4h dt - - - - - - - - when vdd is turned on, por function works and all registers of ak09915 are initialized regardless of vid status. to write data to or to read data from register, vid must be on. ts1, ts2, ts3 , ts4 , tph1, tph2, rr, syt and dt are test register for shipment test. do not access these registers. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 30 - 11.3. detailed description of registers 11.3.1. wia: who i am addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 00 h wia1 0 1 0 0 1 0 0 0 01 h wia2 0 0 0 1 0 0 0 0 wia1[7:0] bits : company id of akm. it is described in one byte and fixed value. 48 h : fixed wia2[7:0] bits : device id of ak09915 . it is described in one byte and fixed value. 10 h : fixed 11.3.2. rsv : reserved addr . register n ame d7 d6 d5 d4 d3 d2 d1 d0 read - only register 02 h rsv rsv 17 rsv 16 rsv 15 rsv 14 rsv 13 rsv 12 rsv 11 rsv 10 rsv [7:0] bits : reserved register for akm. 11.3.3. info: information addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 0 3h info 0 0 0 0 0 0 0 0 info[7:0] bits: administrative information of akm. it is described in one byte and fixed value. 00h: fixed 11.3.4. st1: status 1 addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 10 h st1 hsm 0 0 0 0 0 dor drdy reset 0 0 0 0 0 0 0 0 drdy bit : data ready 0 : normal 1 : data is ready when fifo is disabled (fifo bit = 0 ); drdy bit turns to 1 when data is ready in single measurement mode, continuous measurement mode 1, 2, 3, 4 , 5, 6 or self - test mode. it returns to 0 when any one of st2 register or measurement data register (hxl to tmps) is read. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 31 - when fifo is enabled (fifo bit = 1 ); if the number of stored data set is equal to or more than the number set to wm[ 4 :0] bits, drdy bit turns to 1. if the number of stored data set is less than the number set to wm[ 4 :0] bits, drdy bit turns to 0. dor bit : data overrun 0: normal 1: data overrun when fifo is disabled (fifo bit = 0 ); dor bit turns to 1 when data has been skipped in continuous measurement mode 1, 2, 3 , 4, 5 or 6 . it returns to 0 when any one of st2 register or measurement data register (hxl to tmps) is read. when fifo is enabled (fifo bit = 1 ); if a set of new data is measured when the buffer is full, dor bit turns to 1. if at least one data set is read from the buffer, dor bit turns to 0. hsm bit : i 2 c hs - mode 0: standard/fast mode 1: hs - mode hsm bit turns to 1 when i 2 c bus interface is changed from standard or fast mode to high - speed mode (hs - mode). 11.3.5. hxl to hzh: measurement magnetic data addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 11 h hxl hx7 hx6 hx5 hx4 hx3 hx2 hx1 hx0 12 h hxh hx15 hx14 hx13 hx12 hx11 hx10 hx9 hx8 13 h hyl hy7 hy6 hy5 hy4 hy3 hy2 hy1 hy0 14 h hyh hy15 hy14 hy13 hy12 hy11 hy10 hy9 hy8 15 h hzl hz7 hz6 hz5 hz4 hz3 hz2 hz1 hz0 16 h hzh hz15 hz14 hz13 hz12 hz11 hz10 hz9 hz8 reset 0 0 0 0 0 0 0 0 measurement data of magnetic sensor x - axis/y - axis/z - axis hxl[7:0] bits : x - axis measurement data lower 8 - bit hxh[15:8] bits : x - axis measurement data higher 8 - bit hyl[7:0] bits : y - axis measurement data lower 8 - bit hyh[15:8] bits : y - axis measurement data higher 8 - bit hzl [7:0] bits : z - axis measurement data lower 8 - bit hzh[15:8] bits : z - axis measurement data higher 8 - bit [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 32 - measurement data is stored in twos complement and little endian format. measurement range of each axis is - 32752 to 32752 in 16 - bit output. table 11 . 3 measurement magnetic data format measurement data (each axis) [15:0] bits magnetic flux density [ ] twos complement hex decimal 0111 1111 1111 0000 7ff0 32752 4912 (max.) | | | | 0000 0000 0000 0001 0001 1 0. 1 5 0000 0000 0000 0000 0000 0 0 1111 1111 1111 1111 ffff - 1 - 0. 1 5 | | | | 1000 0000 000 1 0 000 8010 - 32752 - 4912 (min.) when fifo is enabled (fifo bit = 1 ); by accessing hxl register, the oldest data set is passed to the read register from the buffer. reading st2 register is regarded as the finish of reading out one set of data. then the read data set is deleted and the next oldest data set will be ready to be read. if st2 register or hxl register is not read, the same set of data is kept in the read register. when reading out data , always start with hxl register and finish with st2 register. 11.3.6. tmps: dummy addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 17 h tmps 0 0 0 0 0 0 0 0 reset 0 0 0 0 0 0 0 0 tmps[7:0] bits : dummy register 11.3.7. st2: status 2 addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 18 h st2 0 0 0 0 hofl inv 0 0 reset 0 0 0 0 0 0 0 0 hofl bit : magnetic sensor overflow 0: normal 1: magnetic sensor overflow occurred in single measurement mode, continuous measurement mode s (1 to 6) and self - test mode, magnetic sensor may overflow even though measurement data register s are not saturated. in this case, measurem ent data is not correct and hofl bit turns to 1. when measurement data register (hxl to hzh) is updated, hofl bit is updated . refer to 9.4.3.6 for detailed info rmation. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 33 - inv bit : invalid data 0: normal 1: data is invalid inv bit functions only when fifo is enabled (fifo bit = 1 ). if data is read out when there is no data set in the buffer, inv bit is turned to 1 and measurement data register s (hxl to hzh) are forced to fixed value 7fffh. if a set of new data is measured, inv bit turns to 0 . when fifo is disabled (fifo bit = 0 ); st2 register has a role as data reading end register, also. when any of measurement data register (hxl to tmps) is read in continuous measurement mode s (1 to 6) , it means data reading start and taken as data reading until st2 register is read. therefore, when any of measurement data is read, be sure to read st2 register at the end. when fifo is enabled (fifo bit = 1 ); st2 register is a part of one set of data stored in the buffer. if any of data register (hxl to tmps) is read, be sure to read st2 register at the end. if read data set includes magnetic sensor over flow, hofl bit is 1 . if there is no data set in t he buffer, inv bit is 1 . 11.3.8. cntl1: control 1 addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read /write register 30 h cntl1 0 0 nsf wm4 wm3 wm2 wm1 wm0 reset 0 0 0 0 0 0 0 0 nsf bit : noise suppression filter setting 0: disable 1: enable output data from magnetic sensor is filtered to suppress the noise according to the setting. refer to 9.5 for detailed information. do not write 1 in d6 register . wm[ 4 :0] bits : watermark level setting 0000 0 : 1 step 000 0 1: 2 steps 00 0 10: 3 steps | 1 1111 : 32 steps (upper limit) watermark level can be set every 1 step. the upper limit of watermark level is 32 steps (wm[4:0] bits = 1 11 11 ) . it is prohibited to change wm[ 4 :0] bits in any other modes than power - down mode. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 34 - 11.3.9. cntl2: control 2 addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register 31 h cntl2 fifo sdr 0 mode4 mode3 mode2 mode1 mode0 reset 0 0 0 0 0 0 0 0 mode[4:0] bits : operation mode setting 00000: power - down mode 00001: single measurement mode 00010: continuous measurement mode 1 00100: continuous measurement mode 2 00110: continuous measurement mode 3 01000: continuous measurement mode 4 010 1 0: continuous measurement m ode 5 01 10 0: continuous measurement mode 6 10000: self - test mode when each mode is set, ak09915 transits to the set mode. refer to 9.3 for detailed information. if o ther value is set , ak09915 transits to power - down mode automatically. sdr bit : sensor drive setting 0 : low power drive 1 : low noise drive default sdr bit is low power drive ( sdr bit = 0). by writing 1 to sdr bit, ak09915 is switch ed from low power drive to low noise drive . fifo bit : fifo setting 0 : disable 1 : enable by writing 1 to fifo bit, fifo function is enabled. by writing 0 , fifo function is disabled and the buffer is cleared at the same time. fifo function is available only in continuous measurement mode. it is prohibited to enable it other than continuous measurement mode 11.3.10. cntl3: control 3 addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register 32 h cntl3 0 0 0 0 0 0 0 srst reset 0 0 0 0 0 0 0 0 srst bit : soft reset 0: normal 1: reset when 1 is set, all registers are initialized. after reset, srst bit turns to 0 automatically. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 35 - 11.3.11. ts1, ts2, ts3: test addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register 33 h ts1 - - - - - - - - 34 h ts2 - - - - - - - - 35 h ts3 - - - - - - - - reset 0 0 0 0 0 0 0 0 ts1, ts2 and ts3 registers are akm internal test registers. do not access these registers. 11.3.12. i2cdis: i 2 c disable addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register 36 h i2cdis i2cdis7 i2cdis 6 i2cdis 5 i2cdis 4 i2cdis 3 i2cdis 2 i2cdis 1 i2cdis0 reset 0 0 0 0 0 0 0 0 this register disables i 2 c bus interface. i 2 c bus interface is enabled in default. to disable i 2 c bus interface, write 00011011 to i2cdis [7:0] bits . then i 2 c bus interface is disabled. once i 2 c bus interface is disabled, it is impossible to write other value to i2cdis register. to enable i 2 c bus interface, reset ak09915 or input start condition 8 times continuously. 11.3.13. ts4: test addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register 37 h ts4 - - - - - - - - reset 0 0 0 0 0 0 0 0 ts4 register is test register for shipment test. do not access this registers. 11.3.14. asax,asay,asaz: dummy addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read - only register 60h asax 1 0 0 0 0 0 0 0 61h asay 1 0 0 0 0 0 0 0 62h asaz 1 0 0 0 0 0 0 0 reset 1 0 0 0 0 0 0 0 asax, asay and asaz register s are d ummy register s for ensur ing the compatibility with other akm compass. these registers are fixed value (80 h). [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 36 - 11.3.15. tph1,tph2,rr,syt,dt: test addr . register name d7 d6 d5 d4 d3 d2 d1 d0 read/write register c0h tph1 - - - - - - - - c1h tph2 - - - - - - - - c3h syt - - - - - - - - c4h dt - - - - - - - - reset 0 0 0 0 0 0 0 0 ch2 rr - - - - - - - - reset 0 0 0 0 0 0 1 1 tph1, tph2, rr, syt and dt registers are akm internal test registers. do not access these registers. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 37 - 12. example of recommended external connection 12.1. i 2 c bus interface pins of dot circle should be kept non - connected. ak09915 c (top view) interrupt host cpu i 2 c i/f power for i / f vid power 1. 65 v to v dd vdd power 1.7 v to 3.6v 0.1f 0.1f tst2 rstn vid so sda /si n/c n/c scl /sk csb n/c cad0 cad1 vss vdd drdy slave address select cad1 cad0 address vss vss 0 0 0 1 1 0 0 r/w vss v d d 0 0 0 1 1 0 1 r/w v d d vss 0 0 0 1 1 1 0 r/w v d d v d d 0 0 0 1 1 1 1 r/w gpio 4 3 2 1 d c b a [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 38 - 12.2. 4 - wire spi pins of dot circle should be kept non - connected. AK09915C (top view) interrupt host cpu spi i/f power for i/f vid power 1. 65 v to v dd vdd power 1.7 v to 3.6v 0.1f 0.1f tst2 rstn vid so sda /si n/c n/c scl /sk csb n/c cad0 cad1 vss vdd drdy gpio 4 3 2 1 d c b a [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 39 - 13. package 13.1. marking product name: 0991 5 dat e code: x 1 x 2 x 3 x 4 x 5 x1 = id x2 = year code x3 = month code x4x5 = lot 13.2. pin assignment 4 3 2 1 d rstn cad1 cad0 c vid n/c n/c vss b so n/c vdd a sda/si scl/sk csb drdy [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 40 - 13.3. outline dimensions [mm] 13.4. recommended foot print pattern [mm] [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 41 - 14. relationship between the magnetic field and output code the measurement data increases as the magnetic flux density increases in the arrow directions. [ ak0991 5 ] 015006484 - e - 0 2 201 6 / 7 - 42 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any in tellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily hig h levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment use d in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices rela ted to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human li fe, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, f or the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this docu ment, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manu facture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in co mpliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with a pplicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm . |
Price & Availability of AK09915C
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |